View 5962R9582401VQC_7267057.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hs-80c85rh radiation hardened 8-bit cmos microprocessor description the hs-80c85rh is an 8-bit cmos microprocessor fabri- cated using the intersil radiation hardened self-aligned junc- tion isolated (saji) silicon gate technology. latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic scr effect seen in conventional bulk cmos devices. the hs-80c85rh is a functional logic emulation of the hmos 8085 and its instruction set is 100% software com- patible with the hmos device. the hs80c85rh is designed for operation with a single 5 volt power supply. its high level of integration allows the construction of a radiation hardened microcomputer system with as few as three ics (hs- 80c85rh cpu, hs83c55rh rom i/o, and the hs-81c55/ 56rh ram i/o. features ? devices qml quali?ed in accordance with mil-prf-38535 ? detailed electrical and screening requirements are contained in smd# 5962-95824 and intersil qm plan ? radiation hardened epi-cmos - parametrics guaranteed 1 x 10 5 rad(si) - transient upset > 1 x 10 8 rad(si)/s - latch-up free > 1 x 10 12 rad(si)/s ? low standby current 500 m a max ? low operating current 5.0ma/mhz (x 1 input) ? electrically equivalent to sandia sa 3000 ? 100% software compatible with intel 8085 ? operation from dc to 2mhz, post radiation ? single 5 volt power supply ? on-chip clock generator and system controller ? four vectored interrupt inputs ? completely static design ? self aligned junction isolated (saji) process ? military temperature range -55 o c to +125 o c february 1996 spec number 518054 file number 3036.2 pinouts 40 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835, cdip2-t40 top view 42 lead ceramic metal seal flatpack package (flatpack) intersil outline k42.a top view 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 hlda hold ready rd io / m ale wr vdd s1 s0 a15 a14 a13 a12 a11 a10 a9 a8 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 intr int a sod sid trap rst 7.5 rst 6.5 rst 5.5 gnd x1 x2 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 reset out reset in clock out hlda hold ready rd io / m ale wr vdd s1 s0 a15 a14 a13 a12 a11 a10 a9 a8 reset clock gnd out in intr int a sod sid trap rst 7.5 rst 6.5 rst 5.5 x1 x2 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 reset out nc nc 33 32 39 38 37 36 35 34 42 41 31 30 29 28 27 24 23 22 40 26 25 10 11 4 5 6 7 8 9 1 2 12 13 14 15 16 19 20 21 3 17 18
2 hs-80c85rh functional diagram ordering information part number temperature range screening level package 5962r9582401qqc -55 o c to +125 o c mil-prf-38535 level q 40 lead sbdip 5962r9582401qxc -55 o c to +125 o c mil-prf-38535 level q 42 lead ceramic flatpack 5962R9582401VQC -55 o c to +125 o c mil-prf-38535 level v 40 lead sbdip 5962r9582401vxc -55 o c to +125 o c mil-prf-38535 level v 42 lead ceramic flatpack hs1-80c85rh/sample +25 o c sample 40 lead sbdip hs9-80c85rh/sample +25 o c sample 42 lead ceramic flatpack accumu- lator (8) temp reg (8) flag (5) flip flops instruction register (8) arithmetic logic unit (alu) (8) power supply vdd gnd instruction decoder and machine cycle encoding x1 x2 clk gen control status dma reset timing and control address a15-a8 clk out ready rd wr ale s0 s1 io/ m hlda reset in reset out hold buffer (8) address bus b reg (8) d reg (8) h reg (8) stack pointer (16) c reg (8) e reg (8) l reg (8) program counter (16) incrementer address latch (16) decrementer data address buffer (8) ad1-ad0 address bus interrupt control serial i/o control 8-bit internal data bus int a intr rst trap sid sod 5.5 rst 6.5 rst 7.5 register array spec number 518054
3 hs-80c85rh pin description symbol pin number type description a8 - a15 21-28 o address bus: the most significant 8 bits of the memory address or the 8 bits of the i/o address, 3-stated during hold and halt modes and during reset. ad0-7 12-19 i/o multiplexed address/data bus: lower 8 bits of the memory address (or i/o address) appear on the bus during the first clock cycle (t state) of a machine cycle. it then becomes the data bus during the second and third clock cycles. ale 32 o address latch enable: it occurs during the first clock state of a machine cycle and enables the address to get latched into the on-chip latch of peripherals. the falling edge of ale is set to guar- antee setup and hold times for the address information. the falling edge of ale can also be used to strobe the status information. ale is never 3-stated. s0, s1, and io/ m 31, 35, & 36 o machine cycle status: io/ m s1 s0 status 0 0 1 memory write 0 1 0 memory write 1 0 1 i/o write 1 1 0 i/o read 0 1 1 opcode fetch 1 1 1 opcode fetch 1 1 1 interrupt acknowledge t 0 0 halt t x x hold t x x reset t = 3-state (high impedance) x = unspecified s1 can be used as an advanced r/ w status. io/ m, s0 and s1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. the falling edge of ale may be used to latch the state of these lines. rd 34 o read control: a low level on rd indicates the selected memory or i/o device is to be read and that the data bus is available for the data transfer, 3-stated during hold and halt modes and dur- ing reset. wr 33 o write control: a low level on wr indicates the data on the data bus is to be written into the se- lected memory or i/o location. data is set up at the trailing edge of wr, 3-stated during hold and halt modes and during reset. ready 35 i ready: if ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. if ready is low, the cpu will wait an integral number of clock cycles for ready to go high before completing the read or write cycle. ready must conform to specified setup and hold times. hold 39 i hold: indicates that another master is requesting the use of the address and data buses. the cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. internal processing can continue. the processor can regain the bus only after the hold is removed. when the hold is acknowledged, the address, data bus, rd, wr, and io/ m lines are 3-stated. hlda 38 o hold acknowledge: indicates that the cpu has received the hold request and that it will relin- quish the bus in the next clock cycle. hlda goes low after the hold request is removed. the cpu takes the bus one half clock cycle after hlda goes low. spec number 518054
4 hs-80c85rh figure 1. power-on reset circuit intr 10 i interrupt request: is used as a general purpose interrupt. it is sampled only during the next to the last clock cycle of an instruction and during hold and halt states. if it is active, the program counter (pc) will be inhibited from incrementing and an int a will be issued. during this cycle a restart or call instruction can be inserted to jump to the interrupt service routine. the intr is enabled and disabled by software. it is disabled by reset and immediately after an interrupt is accepted. int a 11 o interrupt acknowledge: is used instead of (and has the same timing as) rd during the instruc- tion cycle after an intr is accepted. it can be used to activate an 8259a interrupt chip or some other interrupt port. rst 5.5 rst 6.5 rst 7.5 9 8 7 i restart interrupts: these three inputs have the same timing as intr except they cause an internal restart to be automatically inserted. the priority of these interrupts is ordered as shown in table 6. these interrupts have a higher priority than intr. in addition, they may be individually masked out using the sim instruction. trap 6 i trap: trap interrupt is a non-maskable restart interrupt. it is recognized at the same time as intr or rst 5.5-7.5. it is unaffected by any mask or interrupt enable. it has the highest priority of any interrupt. (see table 6.) reset in 36 i reset in: sets the program counter to zero and resets the interrupt enable and hlda flip-flops. the data and address buses and the control lines are 3-stated during reset and because of the asynchronous nature of reset the processors internal registers and flags may be altered by reset with unpredictable results. reset in is a schmitt-triggered input, allowing connec- tion to an r-c network for power-on reset delay (see figure 1). upon power-up, reset in must remain low for at least 10 clock cycle after minimum vdd has been reached. for proper reset operation after the power-up duration, reset in should be kept low a minimum of three clock periods. the cpu is held in the reset condition as long as reset in is applied. reset out 3 o reset out: reset out indicates cpu is being reset. can be used as a system reset. the signal is synchronized to the processor clock and lasts an integral number of clock periods. x1 x2 1 2 i o x1 and x2: are connected to a crystal, lc, or rc network to drive the internal clock generator. x, can also be an external clock input from a logic gate. the input frequency is divided by 2 to give the processors internal operating frequency. clk 37 o clock: clock output for use as a system clock. the period of clk is twice the x1, x2 input period. sid 5 i serial input data line: the data on this line is loaded into accumulator bit 7 whenever a rim instruction is executed. sod 4 o serial output data line: the output sod is set or reset as specified by the slm instruction. vcc 40 i power: +5v supply. gnd 20 i ground: reference. pin description (continued) symbol pin number type description r1 vdd reset in c1 typical power-on reset rc values ? r1 = 75k w c1 = 1 m f ? values may have to vary due to applied power supply ramp up time. spec number 518054
5 speci?cations hs-80c85rh absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.3v to vcc+0.3v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c typical derating factor. . . . . . . . . . .2.0ma/mhz increase in iddop esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sbdip package. . . . . . . . . . . . . . . . . . . . 45 o c/w 10 o c/w ceramic flatpack package . . . . . . . . . . . 77 o c/w 13 o c/w maximum package power dissipation at +125 o c ambient sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2mw/ o c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . 13.0mw/ o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating supply voltage range (vdd) . . . . . . . +4.75v to +5.25v operating temperature range (t a ) . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +0.8v input high voltage. . . . . . . . . . . . . . . . . . . . . . . . vdd -0.5v to vdd table 1. dc electrical performance characteristics parameter symbol conditions group a subgroups temperature limits units min max input leakage current iih or iil vdd = 5.25v, vi = vdd or gnd 1, 2, 3 -55 o c, +25 o c, or +125 o c -1.0 1.0 m a high level output voltage voh vdd = 4.75v, ioh = -1.0ma 1, 2, 3 -55 o c, +25 o c, or +125 o c vdd -0.5 - v low level output voltage vol vdd = 5.25v, iol = 1.0ma, 1, 2, 3 -55 o c, +25 o c, or +125 o c - 0.5 v static current iddsb vdd = 5.25v, clock out = hi and low 1, 2, 3 -55 o c, +25 o c, or +125 o c - 500 m a operating supply current (note 2) iddop vdd = 5.25v, f = 1mhz (note 2) 1, 2, 3 -55 o c, +25 o c, or +125 o c - 5.0 ma/mhz functional tests ft vdd = 4.75v and 5.25v, tcyc = 500ns, vol vdd/2, voh 3 vdd/2 7, 8a, 8b -55 o c, +25 o c, or +125 o c -- - notes: 1. all devices guaranteed at worst case limits and over radiation. 2. operating supply current (iddop) is proportional to crystal frequency. parts are tested at 1mhz table 2. ac electrical performance characteristics parameter symbol group a subgroups temperature limits units min max clk low time (standard clk loading) t1 9, 10, 11 -55 o c, +25 o c, +125 o c40 - ns clk high time (standard clk loading) t2 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - ns clk rise time tr 9, 10, 11 -55 o c, +25 o c, +125 o c - 115 ns clk fall time tf 9, 10, 11 -55 o c, +25 o c, +125 o c - 115 ns x1 rising to clk rising txkr 9, 10, 11 -55 o c, +25 o c, +125 o c 30 250 ns x1 rising to clk falling txkf 9, 10, 11 -55 o c, +25 o c, +125 o c 50 275 ns a8-15 valid to leading edge of control (note 5) tac 9, 10, 11 -55 o c, +25 o c, +125 o c 300 - ns a0-7 valid to leading edge of control tacl 9, 10, 11 -55 o c, +25 o c, +125 o c 300 - ns a0-15 valid to valid data in tad 9, 10, 11 -55 o c, +25 o c, +125 o c 875 - ns address float after leading edge of read (inta) tafr 9, 10, 11 -55 o c, +25 o c, +125 o c - 70 ns spec number 518054
6 speci?cations hs-80c85rh a8-15 valid before trailing edge of ale (note 5) tal 9, 10, 11 -55 o c, +25 o c, +125 o c75 - ns a0-7 valid before trailing edge of ale tall 9, 10, 11 -55 o c, +25 o c, +125 o c 125 - ns ready valid from address valid tary 9, 10, 11 -55 o c, +25 o c, +125 o c 250 - ns address (a8-15) valid after control tca 9, 10, 11 -55 o c, +25 o c, +125 o c 150 - ns width of control low (rd, wr, inta) edge of ale tcc 9, 10, 11 -55 o c, +25 o c, +125 o c 575 - ns trailing edge of control to leading edge of ale tcl 9, 10, 11 -55 o c, +25 o c, +125 o c60 - ns data valid to trailing edge of write tdw 9, 10, 11 -55 o c, +25 o c, +125 o c 575 - ns hlda to bus enable thabe 9, 10, 11 -55 o c, +25 o c, +125 o c - 375 ns bus float after hlda thabf 9, 10, 11 -55 o c, +25 o c, +125 o c - 375 ns hlda valid to trailing edge of clk thack 9, 10, 11 -55 o c, +25 o c, +125 o c90 - ns hold hold time thdh 9, 10, 11 -55 o c, +25 o c, +125 o c- 0 ns hold setup time to trailing edge of clk thds 9, 10, 11 -55 o c, +25 o c, +125 o c - 300 ns intr hold time tinh 9, 10, 11 -55 o c, +25 o c, +125 o c- 0 ns intr, rst and trap setup time to falling edge of clk tins 9, 10, 11 -55 o c, +25 o c, +125 o c - 375 ns address hold time after ale tla 9, 10, 11 -55 o c, +25 o c, +125 o c75 - ns trailing edge of ale to leading edge of control tlc 9, 10, 11 -55 o c, +25 o c, +125 o c 150 - ns ale low during clk high tlck 9, 10, 11 -55 o c, +25 o c, +125 o c 125 - ns ale to valid data during read tldr 9, 10, 11 -55 o c, +25 o c, +125 o c 675 - ns ale to valid data during write tldw 9, 10, 11 -55 o c, +25 o c, +125 o c - 350 ns ale width tll 9, 10, 11 -55 o c, +25 o c, +125 o c 200 - ns ale to ready stable tlry 9, 10, 11 -55 o c, +25 o c, +125 o c - 175 ns trailing edge of read to re-enabling the ad- dress trae 9, 10, 11 -55 o c, +25 o c, +125 o c 120 - ns read (or inta) to valid data trd 9, 10, 11 -55 o c, +25 o c, +125 o c 375 - ns control trailing edge to leading edge of next control trv 9, 10, 11 -55 o c, +25 o c, +125 o c 550 - ns data hold time after read inta trdh 9, 10, 11 -55 o c, +25 o c, +125 o c- 0 ns ready hold time tryh 9, 10, 11 -55 o c, +25 o c, +125 o c- 0 ns ready setup time to leading edge of clk trys 9, 10, 11 -55 o c, +25 o c, +125 o c 250 - ns data valid after trailing edge of write twd 9, 10, 11 -55 o c, +25 o c, +125 o c 150 - ns leading edge of write to data valid twdl 9, 10, 11 -55 o c, +25 o c, +125 o c - 50 ns notes: 1. output timings are measured with a purely capacitive load, cl = 150pf 2. vdd = 4.75v, vih = 4.25v, vil = 0.8v 3. delay times are measured with a 1mhz clock. an algorithm is used to convert the delays into the ac timings above with a tcyc = 500ns. 4. the ac table is tested as shown above to guarantee the processor system timing. 5. a8 - a15 address specifications also apply to io/m, s0 and s1 except a8 - a15 are undefined during t4-t6 of off cycle whereas io/m, so, and s1 are stable. table 2. ac electrical performance characteristics (continued) parameter symbol group a subgroups temperature limits units min max spec number 518054
7 speci?cations hs-80c85rh table 3. electrical performance characteristics parameter symbol (note 1) conditions temperature limits units min max input capacitance cin vdd = open, f = 1mhz t a = +25 o c - 12 pf i/o capacitance ci/o vdd = open, f = 1mhz t a = +25 o c - 13 pf output capacitance cout vdd = open, f = 1mhz t a = +25 o c - 12 pf note: 1. all measurements referenced to device ground. table 4. post 100k rad electrical performance characteristics note: the post irradiation test conditions and limits are the same as those listed in tables 1 and 2. table 5. burn-in delta parameters (+25 o c; in accordance with smd) table 6. interrupt priority, restart address, and sensitivity name priority address branched to (1) when interrupt occurs type trigger trap 1 24h rising edge and high level until sampled. rst 7.5 2 3ch rising edge (latched) rst 6.5 3 34ch high level until sampled. rst 5.5 4 2ch high level until sampled. intr 5 see note 2 high level until sampled. notes: 1. the processor pushes the pc on the stack before branching to the indicated address. 2. the address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. table 7. bus timing specification as a t cyc dependent symbol hs-8oc85rh symbol hs-8oc85rh tal (1/2)t- 175 minimum tcc (3/2 + n)t - 175 minimum tla (1/2)t- 175 minimum tcl (1/2)t - 190 minimum tll (1/2)t-50 minimum tary (3/2)t - 500 maximum tlck (1/2)t- 125 minimum thack (1/2)t - 160 minimum tlc (1/2)t- 100 minimum thabf (1/2)t +125 maximum tad (5/2 + n)t - 375 maximum thabe (1/2)t +125 maximum trd (3/2 + n)t - 375 maximum tac (2/2)t - 200 minimum trae (1/2)t- 130 minimum t1 (1/2)t-210 minimum tca (1/2)t - 100 minimum t2 (1/2)t- 150 minimum tdw (3/2 + n)t - 175 minimum trv (3/2)t - 200 minimum twd (1/2)t-100 minimum tldr (4/2)t - 325 maximum note: n is equal to the total wait states t = tcyc spec number 518054
8 hs-80c85rh waveforms figure 2. clock figure 3. read figure 4. write txkr txkf tcyc t1 tr t2 tf clk x 1 input output address a 8-15 address clk ad 0 -ad 7 ale rd/inta tal tll tla tafr tlck tad tldr tlc tac trd tcc tcl trae tca trdh data in t1 t2 t3 t1 address tdw a 8-15 tcc address tla tll tal tac tlc tcl twd tca tldw tlck twdl data out t1 t3 t2 t1 clk ad 0 -ad 7 ale wr spec number 518054
9 hs-80c85rh figure 5. hold figure 6. read operation with wait cycle (typical) - same ready timing applies to write figure 7. interrupt and hold waveforms (continued) thds t2 clk hold hlda bus (address, controls) thdh thack thabf t2 thold thold t1 thabe address address data in tac tary tlry tlc tryh trys trys tryh tcc trd tldr tafr tla tll tal tad tlck t1 t2 twait t3 t3 tcl trae trdh tca clk a 8-15 ad 0 -ad 7 ale rd/int a ready note 1: ready must remain stable during setup and hold times. thabe thabf thack thdh thds tinh tins intr hold hlda intr rd call inst. a0-7 a8-15 t1 t2 t3 t4 t5 t6 thold t1 t2 bus floating ? ? io/m is also floating during this time. spec number 518054
10 hs-80c85rh table 9. instruction set summary mnemonic instruction code operations description d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 move, load, and store movr1, r2 0 1 d d d s s s move register to register mov m.r 01110sss move register to memory mov r.m 0 1 d d d 1 1 0 move memory to register mvl r 0 0 d d d 1 1 0 move immediate register mvl m 00110110 move immediate memory lxl b 00000001 load immediate register pair b & c lxl d 00010001 load immediate register pair d & e lxl h 00100001 load immediate register pair h & l stax b 00000010 store a indirect stax d 00010010 store a indirect ldax b 00001010 load a indirect ldax d 00011010 load a indirect sta 00110010 store a direct lda 00111010 load a direct shld 00100010 store h & l direct lhld 00101010 load h & l direct xchg 11101011 exchange d & e, h & l registers stack ops push b 11000101 push register pair b & c on stack push d 1 1 010101 push register pair d & e on stack push h 1 1 1 0 0 1 0 1 push register pair h & l on stack push psw 1 1 110101 push a and flags on stack cz 11001100 call on zero cnz 11000100 call on no zero cp 11110100 call on positive cm 11111100 call on minus cpe 11101100 call on parity even cpo 11100100 call on parity odd return ret 11001001 return rc 11011000 return on carry rnc 11010000 return on no carry rz 11001000 return on zero rnz 11000000 return on no zero rp 11110000 return on positive rm 11111000 return on minus rpe 11101000 return on parity even rpo 11100000 return on parity odd restart rst 1 1 a a a 1 1 1 restart input/output in 11011011 input out 11010011 output increment and decrement inr r 0 0 d d d 1 0 0 increment register dcr r 0 0 d d d 1 0 1 decrement register inr m 00110100 increment memory dcr m 00110101 decrement memory inx b 00000011 increment b & c registers inx d 00010011 increment d & e registers pop b 11000001 pop register pair b & c off stack pop d 11010001 pop register pair d & e off stack pop h 11100001 popregister pair h & l off stack pop psw 11110001 pop a and flags off stack xthl 11100011 exchange top ot stack, h & l sphl 11111001h & l to stack pointer lxi sp 00110001 load immediate stack pointer inx sp 00110011 increment stack pointer dcx sp 00111011 decrement stack pointer jump jmp 11000011 jump unconditional jc 11011010 jump on carry jnc 11010010 jump on no carry jz 11001010 jump on zero jnz 11000010 jump on no zero jp 11110010 jump on positive jm 11111010 jump on minus mnemonic instruction code operations description d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 spec number 518054
11 hs-80c85rh jpe 11101010 jump on parity even jpo 11100010 jump on parity odd pchl 11101001h & l to program counter call call 11001101 call unconditional cc 11011100 call on carry cnc 11010100 call on no carry logical ana r 10100sss and register with a xra r 10101sss exclusive or register with a ora r 10110sssor register with a cmp r 10111sss compare register with a ana m 10100110 and memory with a xra m 10101110 exclusive or mem- ory with a ora m 10110110or memory with a cmp m 10111110 compare memory with a ani 11100110 and immediate with a xri 11101110 exclusive or immediate with a orl 11110110or immediate with a cpl 11111110 compare immedi- ate with a rotate rlc 00000111 rotate a left rrc 00001111 rotate a right ral 00010111 rotate a left through carry rar 00011111 rotate a right through carry inx h 00100011 increment h & l registers dcx b 00001011 decrement b & c dcx d 00011011 decrement d & e dcx h 00101011 decrement h & l add add r 10000sss add register to a adc r 10001sss add register to a with carry add m 1 0 c 00110 add memory to a mnemonic instruction code operations description d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 adc m 10001110 add memory to a with carry adl 11000110 add immediate to a acl 11001110 add immediate to a with carry dad b 00001001 add b & c to h & l dad d 00011001 add d & e to h & l dad h 00101001 add h & l to h & l dad sp 00111001 add stack pointer to h&l subtract sub r 10010sss subtract register from a sbb r 10011sss subtract register from a with borrow sub m 10010110 subtract memory from a sbb m 10011110 subtract memory from a with borrow sul 11010110 subtract immedi- ate from a sbl 11011110 subtract immedi- ate from a with borrow specials cma 00101111 complement a stc 00110111 set carry cmc 00111111 complement carry daa 00100111 decimal adjust a control el 11111011 enable interrupts di 11110011 disable interrupt nop 00000000 no-operation hlt 01110110 halt rim 00100000 read interrupt mask slm 00110000 set interrupt mask notes: 1. dds or sss: b000, c001, d010, e011, h100, l101, memory 110, a111 2. two possible cycle times (6/12) indicate instruction cycles dependent on condi- tion flags. ? all mnemonics copyrighted ? intel corporation 1976 mnemonic instruction code operations description d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 table 9. instruction set summary (continued) spec number 518054
12 hs-80c85rh functional description the hs-80c85rh is a complete 8-bit parallel central pro- cessing unit implemented in a self aligned, silicon gate, cmos technology. its static design allows the device to be operated at any external clock frequency from a maximum of 4mhz down to dc. the processor clock can be stopped in either the high or low state and held there inde?nitely. this type of operation is especially useful for system debug or power critical applications. the device is designed to ?t into a minimum system of three ics: cpu (hs-80c85rh), ram/ io (hs-81c55/56rh) and rom/io chip (hs-83c55rh). since the hs-80c85rh is implemented in cmos, all of the advantages of cmos technology are inherent in the device. these advantages include low standby and operating power, high noise immunity, moderately high speed, wide operating temperature range, and designed-in radiation hardness. thus the hs-80c85rh is ideal for weapons and space applications. the hs-80c85rh has twelve addressable 8-bit registers. four of them can function only as two 16-bit register pairs. six others can be used interchangeably as 8-bit registers or as 16-bit register pairs. the hs-80c85rh register set is as follows: the hs-80c85rh uses a multiplexed data bus. the address is split between the higher 8-bit address bus and the lower 8-bit address/data bus. during the ?rst t state (clock cycle) of a machine cycle the low order address is sent out on the address/data bus. these lower 8 bits may be latched externally by the address latch enable signal (ale). during the rest of the machine cycle the data bus is used for memory or i/o data. the hs-80c85rh provides rd, wr, s0, s1, and io/ m sig- nals for bus control. an interrupt acknowledge signal ( int a) is also provided. hold and all interrupts are synchronized with the processors internal clock. the hs-80c85rh also provides serial input data (sid) and serial output data (sod) lines for simple serial interface. in addition to these features, the hs-80c85rh has three maskable, vector interrupt pins, one nonmaskable trap interrupt, and a bus vectored interrupt, intr. interrupt and serial i/o the hs-80c85rh has 5 interrupt inputs: intr, rst 5.5, rst 6.5, rst 7.5, and trap intr is maskable (can be mnemonic register contents acc or a accumulator 8 -bits pc program counter 16-bit address bc, de, hl general-purpose registers; data pointer(hl) 8-bits x 6 or 16-bits x 3 sp stack pointer 16-bit address flags or f flag register 5 flags (8-bit space) enabled or disabled by el or dl software instructions), and causes the cpu to fetch in an rst instruction, externally placed on the data bus, which vectors a branch to any one of eight ?xed memory locations (restart addresses). the deci- mal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. any of these addresses may be used to store the ?rst instruction(s) of a routine designed to service the requirements of an interrupting device. since the (rst) is a call, completion of the instruction also stores the old program counter contents on the stack. each of the three restart inputs, 5.5, 6.5, and 7.5, has a programma- ble mask. trap is also a restart interrupt but it is nonmaskable. the three maskable interrupts cause the internal execution of restart (saving the program counter in the stack and branching to the restart address) if the interrupts are enabled and if the interrupt mask is not set. the non- maskable trap causes the internal execution of a restart vector independent of the state of the interrupt enable or masks. (see table 9.) there are two different types of inputs in the restart interrupts. rst 5.5 and rst 6.5 are high level-sensitive and are recognized with the same timing as intr. rst 7.5 is rising edge sensitive. for rst 7.5, only a pulse is required to set an internal ?ip?op which generates the internal interrupt request (a normally high level signal with a low going pulse is recom- mended for highest system noise immunity). the rst 7.5 request ?ip-?op remains set until the request is serviced. then it is reset automatically. this ?ip-?op may also be reset by using the slm instruction or by issuing a reset in to the 80c85rh. the rst 7.5 internal ?ip-?op will be set by a pulse on the rst 7.5 pin even when the rst 7.5 interrupt is masked out. the status of the three rst interrupt masks can only be affected by the sim instruction and reset in. the interrupts are arranged in a ?xed priority that determines which interrupt is to be recognized if more than one is pending as follows: trap-highest priority, rst 7.5, rst 6.5, rst 5.5, intr-lowest priority. this priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. rst 5.5 can interrupt an rst 7.5 routine if the interrupts are re-enabled before the end of the rst 7.5 routine. the trap interrupt is useful for catastrophic events such as power failure or bus error. the trap input is recognized just as any other interrupt but has the highest priority. it is not affected by any ?ag or mask. the trap input is both edge and level sensitive. the trap input must go high and remain high until it is acknowledged. it will not be recognized again until it goes low, then high again. this avoids any false triggering due to noise or logic glitches. figure 8illustrates the trap interrupt request circuitry within the hs-80c85rh. note that the servicing of any interrupt (trap, rst 7.5, rst 6.5, rst 5.5, intr) disables all future interrupts (except traps) until an ei instruction is executed. spec number 518054
13 hs-80c85rh figure 8. trap and reset in circuit the trap interrupt is special in that is disables interrupts, but preserves the previous interrupt enable status. perform- ing the ?rst rim instruction following a trap interrupt allows you to determine whether interrupts were enabled or disabled prior to the trap. all subsequent rim instructions provide current interrupt enable status. performing a rim instruction following intr, or rst 5.5-7.5 will provide current interrupt enable status, revealing that interrupts are disabled. the serial i/o system is also controlled by the rim and sim instructions. sid is read by rim, and sim sets the sod data. driving the x1 and x2 inputs you may drive the clock inputs of the hs-80c85rh with a crystal, an lc tuned circuit, an rc network, or an external clock source. the driving frequency may be any value from dc to 4mhz and must be twice the desired internal clock frequency. the following guidelines should be observed when a crystal is used to drive the hs-80c85rh clock input: 1. a 20pf capacitor should be connected from x2 to ground to assure oscillator start-up at the correct frequency. vdd reset in trap external trap interrupt request trap interrupt request internal trap acknowledge inside the 80c85rh schmitt trigger clear clk d f/f d q reset trap f.f. 2. a 10m w resistor is required between x1 and x2 for bias point stabilization. in addition, the crystal should have the following characteristics: 1) parallel resonance at twice the desired internal clock frequency 2) cl (load capacitance) 30pf 3) cs (shunt capacitance) 7pf 4) rs (equivalent shunt resistance) 75 w 5) drive level: 10mw 6) frequency tolerance: 0.005% (suggested) a parallel-resonant lc circuit may be used as the frequency- determining network for the hs-80c85rh, providing that its frequency tolerance of approximately 10% is acceptable. the components are chosen from the formula: 1 f = 2 p? l (cext + cint) to minimize variations in frequency, it is recommended that you choose a value for cext that is at least twice that of cint, or 30pf. the use of an lc circuit is not recommended for frequencies higher than approximately 4mhz. an rc circuit may be used as the frequency-determining network for the hs-80c85rh if maintaining a precise clock frequency is of no importance. variations in the on-chip tim- ing generation can cause a wide variation in frequency when using the rc mode. its advantage is its low component cost. the driving frequency generated by the circuit shown is approximately 3mhz. it is not recommended that frequen- cies greatly higher or lower than this be attempted. figure 9 shows the recommended clock driver circuits. for driving frequencies up to and including 4mhz you may supply the driving signal to x1 and leave x2 open-circuited (figure 9d). a.) quartz crystal clock driver c.) rc circuit clock driver b.) lc tuned circuit clock driver d.) 0-4mhz input frequency external clock driver circuit figure 9. clock driver circuits 20pf rext = 10m w x2 x1 1 2 cint = 15pf 80c85rh 20pf -6k x2 x1 1 2 80c85rh cext x2 x1 1 2 cint = 15pf 80c85rh lext x2 x1 low time > 60ns ? ? x2 left floating spec number 518054
14 hs-80c85rh hs-80c85rh caveats 1. an important caveat that is applicable to cmos devices in gen- eral is that unused inputs should never be left ?oating. this rule also applies to inputs connected to a tri- state bus. the need for external pull-up resistors during tri-state bus conditions is elimi- nated by the presence of regenerative latches on the following hs-80c85rh output pins: ad0-ad7, a8-a15, and io/m. figure 10 depicts an output and corresponding regenerative latch. when the output driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was be- fore the tri-state condition. a transient drive current of approxi- mately 1.0ma at 0.5 vdd for 10nsec is required to switch the latch. thus, cmos device inputs connected to the bus are not allowed to ?oat during tri-state conditions. 2. the rd and wr pins of the hs-80c85rh contain internal dy- namic pull-up transistors to avoid spurious selection of memory devices when the rd and wr pins assume the high impedance state. this eliminates the need for external resistive pull-ups on these pins. 3. the reset in and x1 inputs on the hs-80c85rh are schmit trigger inputs. this eliminates the possibility of internal oscilla- tions in response to slow rise time input signals at these pins. 4. a high frequency bypass capacitor of approximately 0.1 m f should be connected between vdd and gnd to shunt power supply transients. 5. the hs-80c85rh is functional within 10 input clock cycles after application of power (assuming that reset has been asserted from power-on). start up conditions in the crystal controlled oscillator mode must also account for the characteristics of the oscillator. generating an hs-80c85rh wait state if your system requirements are such that slow memories or peripheral devices are being used, the circuit shown in figure 11 may be used to insert one wait state in each hs-80c85rh machine cycle. the d ?ip-?ops should be chosen so that: 1. clk is rising edge-triggered 2. clear is low-level active. the ready line is used to extend the read and write pulse lengths so that the 80c85rh can be used with slow mem- ory. hold causes the cpu to relinquish the bus when it is through with it by ?oating the address and data buses. figure 10. output driver and latch for pins ado-ad7, a8-a15 and io/ m. figure 11. generation of a wait state for hs-80c85rh cpu. output driver regenerative latch output pin clear clk d f/f d ale ? vdd 80c85rh clk output q to 80c85rh ready input clk d f/f d q ? ale and clk (out) should be buffered if clk input of latch exceeds 80c85rh iol or ioh. system interface the hs-80c85rh family includes memory components, which are directly compatible to the hs-8oc8srh cpu. for example, a system consisting of the three radiation- hardened chips, hs-80c85rh, hs-81c56rh, and hs-83c55rh will have the following features: 1. 2k bytes rom 2. 256 bytes ram 3. 1 timer/counter 4. 4 8-bit i/o ports 5. 1 6-bit i/o port 6. 4 interrupt levels 7. serial in/serial out ports this minimum system, using the standard i/o technique is as shown in figure 12. in addition to standard 1/0, the memory mapped i/o offers an ef?cient i/o addressing technique. with this technique, an area of memory address space is assigned for i/o address, thereby, using the memory address for i/o manipulation. figure 13 shows the system con?guration of memory mapped i/o using hs-80c85rh. the hs-80c85rh cpu can also interface with the standard radiation-hardened memory that does not have the multiplexed address/data bus. it will require use of the hs-82c12rh (8-bit latch) as shown in figure 14. figure 12. hs-80c85rh minimum system (standard i/o technique) trap rst 7.5 rst 6.5 rst 5.5 intr int a addr addr/ ale rd wr io/ m rdy clk data x2 x1 hold hlda sod sid s1 s0 reset in hs-80c85rh vss vdd vss vdd ce wr rd ale data/ addr io/ m reset port a port b port c in timer out (8) (8) (6) (8) (8) iow rd ale ce data/ addr io/ m reset port a port b (8) (8) a0-10 rdy clk ior vdd vdd vss vdd ? optional connection ? out reset hs-81c56rh hs-83c55rh spec number 518054
15 hs-80c85rh figure 13. hs-80c85rh minimum system (memory mapped i/o) figure 14. hs-80c85rh system (using standard memories) hs-80c85rh reset wr ale ce io/ m ad0-7 a8-15 vdd ? optional connection hs-81c56rh hs-83c55rh timer out rd (ram + i/o + counter/timer) ad0-7 ale rd wr io/ m clk reset out ready a8-10 ad0-7 ce io/ m ale rd iow clk rst ? rdy (rom +i/o) (8) (8) (8) (8) (6) ? timer in trap rst 7.5 rst 6.5 rst 5.5 intr int a addr addr/ ale rd wr io/ m rdy clk data x2 x1 hold hlda sod sid s1 s0 reset in hs-80c85rh vss vdd io/ m (cs) wr rd standard data addr (cs) (8) (8) clk reset io/ m (cs) wr data standard i/o ports, controls rd addr vdd out reset hs-82c12rh memory (16) i/o vdd vdd spec number 518054
16 hs-80c85rh basic system timing the hs-80c85rh has a multiplexed data bus. ale is used as a strobe to sample the lower 8-bits of address on the data bus. figure 15 shows an instruction fetch, memory read and i/o write cycle (as would occur during processing of the out instruction). note that during the i/o write and read cycle that the i/o port address is copied on both the upper and lower half of the address. there are seven possible types of machine cycles. which of these seven takes place is de?ned by the status of the three status lines (lo/ m, s1, s0) and the three control signals ( rd, wr, and int a). (see table 10.) the status lines can be used as advanced controls (for device selection, for exam- ple), since they become active at the t1 state, at the outset of each machine cycle. control lines rd and wr are used as command lines since they become active when the trans- fer of data is to take place. table 10. hs-80c85rh machine cycle chart machine cycle status control io/ ms1s0 rd wr int a opcode fetch (of) 0 1101 1 memory read (mr) 0 1001 1 memory write (mw) 0 0110 1 i/o read (ior) 1 1001 1 i/o write (iow) 1 0110 1 acknowledge of intr (ina) 1 1111 0 bus idle (bi) dad ack. of 0 1011 1 rst, trap 1 1111 1 halt ts 0 0 ts ts 1 a machine cycle normally consists of three t states, with the exception of opcode fetch, which normally has either four or six t states (unless wait or hold states are forced by the receipt of ready or hold inputs). any t state must be one of ten possible states, shown in table 11. table 11. hs-80c85rh machine state chart ma- chine state status & buses control s1, s0 io/ m a8-15 ad0-7 rd,wr int a ale t1 xxx x 1 11 ? t2 xxx x x x0 twait x x x x x x 0 t3 xxx x x x0 t4 1 0 ?? xts 1 10 t5 1 0 ?? xts 1 10 t6 1 0 ?? xts 1 10 treset x ts ts ts ts 1 0 thalt 0 ts ts ts ts 1 0 thold x ts ts ts ts 1 0 0 = logic 0 1 = logic 1 ts = high impedance x = unspeci?ed ? ale not generated during 2nd and 3rd machine cycles of dad instruction. ?? io/m = 1 during t4, t6 of ina machine cycle. figure 15. 80c85rh basic system timing m1 m3 m2 t1 t2 t3 t4 t1 t2 t3 t1 t2 t3 t clk a8-a15 ad0-7 ale rd wr io/ m status pch (high order address) (pc + 1)h io port io port (pc+1)l pcl (low order address) data from memory (instruction) data from memory (i/o port address) data to memory or peripheral s1-s0 (fetch) 10 (read) 01 write 11 spec number 518054
17 hs-80c85rh metallization topology die dimensions: 229 mils x 240 mils x 14 mils 1 mil metallization: type: sial thickness: 11k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? metallization mask layout hs-80c85rh trap (6) rst 7.5 (7) rst 6.5 (8) rst 5.5 (9) intr (10) int a (11) ad0 (12) ad1 (13) ad2 (14) ad3 (15) ad4 (16) ad5 (17) ad6 (18) ad7 (19) gnd (20) a8 (21) a9 (22) a10 (23) a11 (24) (5) sid (4) sod (3) reset out (2) x2 (1) x1 (40) vdd (39) hold (38) hlda (37) clock out (36) reset in (35) ready (34) io/ m (33) s1 (32) rd (31) wr (30) ale (29) s0 (28) a15 (27) a14 (26) a13 (25) a12 spec number 518054
18 hs-80c85rh spec number 518054 notes: 1. index area: a notch or a pin one identi?cation mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identi?cation shall not be used as a pin one identi?cation mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identi?cation mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and ?nish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the ?nished lead surfaces, when solder dip or tin plate lead ?nish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead ?nish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. 11. the basic lead spacing is 0.050 inch (1.27mm) between center lines. each lead centerline shall be located within 0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (n) lead. e e1 d s1 b q e2 a c 1 a a m c1 b1 (c) (b) section a-a base lead finish metal m e n l k42.a top brazed 42 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a - 0.100 - 2.54 - b 0.017 0.025 0.43 0.64 - b1 0.017 0.023 0.43 0.58 - c 0.007 0.013 0.18 0.33 - c1 0.007 0.010 0.18 0.25 - d 1.045 1.075 26.54 27.31 3 e 0.630 0.650 16.00 16.51 - e1 - 0.680 - 17.27 3 e2 0.530 0.550 13.46 13.97 - e 0.050 bsc 1.27 bsc 11 k----- l 0.320 0.350 8.13 8.89 - q 0.045 0.065 1.14 1.65 8 s1 0.000 - 0.00 - 6 m - 0.0015 - 0.04 - n42 42- rev. 0 6/17/94 packaging
19 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hs-80c85rh spec number

▲Up To Search▲

Price & Availability of 5962R9582401VQC

	To Download 5962R9582401VQC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .